Yao LU (陆 瑶) Ph.D. Candidate Department of Electronic & Computer Engineering The Hong Kong University of Science and Technology Supervisor: Prof. Zhiyao Xie Email:yludf[at]connect.ust.hk

Biography

I am a Ph.D. candidate in the Department of Electronic and Computer Engineering at the Hong Kong University of Science and Technology (HKUST), under the supervision of Prof. Zhiyao Xie. Prior to that, I obtained my Master's degree from Fudan University under the supervision of Prof. Lingli Wang and bachelor's degree from Southeast University. I am currently a visiting scholar at the University of Minnesota, working with Prof. Yu (Kevin) Cao on 3D IC power/thermal analysis.

My research focuses on AI for EDA and 3D IC power/thermal analysis.

Research Interest

• AI for EDA and LLM-Aided Hardware Design

• 3D IC Power/Thermal Analysis and Advanced Packaging

• Learning-Based RTL/Netlist/Layout Analysis for Design Automation

• Architecture-Level Power Modeling and Optimization

Publication

• Y. Lu, Z. Guo, Q. Zhang, S. Liu, W. Fang, W. Li, Z. Xie, “COOL: A Cooling-Aware Point Transformer Framework for Thermal Prediction in Advanced 3D/3.5D IC Packaging”, ACM/IEEE Design Automation Conference (DAC), 2026.

• W. Li*, Y. Lu*, W. Fang, Y. Zhu, Z. Guo, J. Wang, M. Li, Q. Zhang, Z. Xie, “A Self-Supervised and Cross-Design Netlist Power Model for Time-Based Layout Power Analysis”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2026.

• S. Liu*, Y. Lu*, W. Fang, J. Wang, Z. Xie, “SynC-LLM: Generation of Large-Scale Synthetic Circuit Code with Hierarchical Language Models”, Conference on Empirical Methods in Natural Language Processing (EMNLP), Main, 2025.

• W. Li*, Y. Lu*, W. Fang, J. Wang, Q. Zhang, Z. Xie, “ATLAS: A Self-Supervised and Cross-Stage Netlist Power Model for Fine-Grained Time-Based Layout Power Analysis”, ACM/IEEE Design Automation Conference (DAC), 2025.

• S. Liu*, Y. Lu*, W. Fang*, M. Li, Z. Xie, “OpenLLM-RTL: Open Dataset and Benchmark for LLM-Aided Design RTL Generation”, IEEE/ACM International Conference on Computer Aided Design (ICCAD), 2024. (Invited Paper)

• Y. Lu*, Q. Zhang*, Z. Xie, “Unleashing Flexibility of ML-based Power Estimators Through Efficient Development Strategies”, 29th ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), 2024. (Best Paper Nomination)

• Y. Lu*, S. Liu*, Q. Zhang, Z. Xie, “RTLLM: An open-source benchmark for design rtl generation with large language model”, 29th Asia and South Pacific Design Automation Conference (ASP-DAC), 2024.

• Y. Lu, J. Zhang, S. Zheng, Z. Li, L. Wang, “Low Error-Rate Approximate Multiplier Design for DNNs with Hardware-Driven Co-Optimization”, IEEE International Symposium on Circuits and Systems (ISCAS), 2022.

• Y. Dai*, S. Liu*, Y. Lu*, H. Zhou, SR. Rasoulinezhad, PHW. Leong, L. Wang, “APIR-DSP: An approximate PIR-DSP architecture for error-tolerant applications”, International Conference on Field-Programmable Technology (ICFPT), 2021.

• Q. Zhang, Y. Lu, S. Liu, M. Li, C. Zhang, D. Wang, Z. Xie, “G-Power: Architecture-level GPU Power Modeling with Aggregated Knowledge Foundations from Known GPUs”, ACM/IEEE Design Automation Conference (DAC), 2026.

• W. Li, Y. Wu, Z. Guo, Y. Lu, W. Fang, M. Li, Z. Xie, “LEAP: A Self-Supervised Per-Cycle Toggle Propagation Model Supports Fast, Transferable, and Early Analysis of Layout Power”, ACM/IEEE Design Automation Conference (DAC), 2026.

• Y. Zhu, W. Fang, Y. Lu, S. Liu, Y. Zhu, Q. Zhang, Z. Xie, “MFSPart: A Generalized Partitioning Framework for Multi-FPGA Systems and Its Ensemble-Based Extension”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2026.

• Q. Zhang, S. Liu, Y. Lu, M. Li, Z. Xie, “ReadyPower: A Reliable, Interpretable, and Handy Architectural Power Model Based on Analytical Framework”, 31st Asia and South Pacific Design Automation Conference (ASP-DAC), 2026.

• Q. Zhang, Y. Lu, M. Li, S. Liu, Z. Xie, “ArchPower: Dataset for Architecture-Level Power Modeling of Modern CPU Design”, Advances in Neural Information Processing Systems (NeurIPS), D&B Track, 2025.

• J. Wang, S. Liu, Y. Lu, Z. Xie, “HLSDebugger: Identification and Correction of Logic Bugs in HLS Code with LLM Solutions”, IEEE/ACM International Conference on Computer Aided Design (ICCAD), 2025.

• W. Fang, J. Wang, Y. Lu, S. Liu, Z. Xie, “GenEDA: Towards Generative Netlist Functional Reasoning via Cross-Modal Circuit Encoder-Decoder Alignment”, IEEE/ACM International Conference on Computer Aided Design (ICCAD), 2025.

• M. Li, Q. Zhang, Y. Gao, W. Fang, Y. Lu, Y. Ren, Z. Xie, “Profile-Guided Temporal Prefetching”, International Symposium on Computer Architecture (ISCA), 2025.

• Q. Zhang, Y. Lu, M. Li, Z. Xie, “AutoPower: Automated Few-Shot Architecture-Level Power Modeling by Power Group Decoupling”, ACM/IEEE Design Automation Conference (DAC), 2025.

• W. Fang, W. Li, S. Liu, Y. Lu, H. Zhang, Z. Xie, “NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph”, ACM/IEEE Design Automation Conference (DAC), 2025.

• S. Liu, M. Li, Y. Lu, Q. Zhang, Z. Xie, “Towards Big Data in AI for EDA Research: Generation of New Pseudo Circuits at RTL Stage”, 30th Asia and South Pacific Design Automation Conference (ASP-DAC), 2025.

• Q. Zhang, M. Li, Y. Lu, Z. Xie, “FirePower: Towards a Foundation with Generalizable Knowledge for Architecture-Level Power Modeling”, 30th Asia and South Pacific Design Automation Conference (ASP-DAC), 2025.

• S. Liu, W. Fang, Y. Lu, J. Wang, Q. Zhang, H. Zhang, Z. Xie, “RTLCoder: Fully open-source and efficient llm-assisted rtl code generation technique”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2024.

• W. Fang, Y. Lu, S. Liu, Q. Zhang, C. Xu, LW. Wills, H. Zhang, Z. Xie, “Transferable pre-synthesis ppa estimation for rtl designs with data augmentation techniques”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2024.

• S. Liu, W. Fang, Y. Lu, Q. Zhang, H. Zhang, Z. Xie, “RTLCoder: Outperforming gpt-3.5 in design rtl generation with our open-source dataset and lightweight solution”, IEEE LLM Aided Design Workshop (LAD), 2024. (Best Paper Nomination)

• W. Fang, Y. Lu, S. Liu, Q. Zhang, C. Xu, LW. Wills, H. Zhang, Z. Xie, “MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design”, IEEE/ACM International Conference on Computer Aided Design (ICCAD), 2023.

• Z. Li, S. Zheng, J. Zhang, Y. Lu, J. Gao, J. Tao, L. Wang, “Adaptable Approximate Multiplier Design Based on Input Distribution and Polarity”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2022.

• S. Zheng, Z. Li, Y. Lu, J. Gao, J. Zhang and L. Wang, “HEAM: High-Efficiency Approximate Multiplier optimization for Deep Neural Networks”, IEEE International Symposium on Circuits and Systems (ISCAS), 2022.

Education

• Ph.D., Department of ECE, The Hong Kong University of Science and Technology (HKUST), Aug/2023 - Now

• M.Eng., State Key Laboratory of ASIC & System, Fudan University (FDU), Sep/2020 - Jun/2023

• B.Eng., School of Electronic Science and Engineering, Southeast University (SEU), Aug/2016 - Jun/2020

Experience

Huawei Shanghai, China

• Research Intern, Jul. 2022 - May. 2023

NVIDIA Shanghai, China

• ASIC PD Intern, Jul. 2021 - Sept. 2021